Hardware architecture of a wavelet based multiple line addressing driving system for passive matrix displays

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding architecture. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression. 1. Objectives and Background The idea of integration of the scalable video coding architecture with the wavelet based passive matrix display addressing architecture saves the computation of an IDWT (Inverse Discrete Wavelet Transform) for each video frame [1]. Hence it reduces the power consumption of portable devices. The input video frame Bvideo,i of the scalable video decoder enters the FPGA, where a matrix multiplication is performed with the matrix (Fn )according to equation (1), to obtain the column voltage matrix Gvideo,i. T -1 video,i video,i n G =cB (F ) (1) The analysis matrix Fn is composed of symmetric biorthogonal 9/7 wavelet coefficients of dimension n*n, where c is the scaling factor. A necessary condition to calculate the correct column voltages is that the decoded wavelet video frame Bvideo,i needs to be equal to the encoded one given by equation (2). The matrix Xi is the original video frame i and the matrix Fm, the analysis matrix composed of symmetric biorthogonal 9/7 wavelet coefficients of size m*m. T -1 video,i m i n B =F X (F ) (2) Simulated Display Voltages derived from the 2 D wavelet decomposition on level 1 50 100 150 200 250 300 350 50